QE Reduction due to Pixel Vignetting in CMOS Image Sensors

CMOS image sensor designers take advantage of technology scaling either by reducing pixel size or by adding more transistors to the pixel. In both cases, the distance from the chip surface to the photodiode increases relative to the photodiode planar dimensions. As a result, light must travel through an increasingly deeper and narrower "tunnel" before it reaches the photodiode. This is especially problematic for light incident at oblique angles; the narrow tunnel walls cast a shadow on the photodiode, which in turn severely reduces its effective QE. We refer to this phenomenon as pixel vignetting. The paper presents experimental results from a 640 x 512 CMOS image sensor fabricated using a O.35j 4-layer metal CMOS process that shows significant QE reduction of up to 50% for off-axis relative to on-axis pixels. Using simple geometric models of the sensor and the imaging optics, we compare the QE for on and off-axis pixels. We find that our analysis results support the hypothesis that the experimentally observed QE reduction is indeed due to pixel vignetting. We show that pixel vignetting becomes more severe as CMOS technology scales, even for a 2-layer metal APS pixel. Finally, we briefly discuss several potential solutions to the pixel vignetting problem.